1. Field of the Invention
The present invention relates to a voltage detection circuit for detecting whether a voltage to be detected has a high voltage level or a low voltage level.
2. Description of the Prior Art
One type of semiconductor memory device, uses, as a memory element, MOS field effect transistors having a floating gate electrode and a control gate electrode. When information is written in the device, that is, in a program mode, a voltage, for example, of about +25 volts, should be supplied to a control gate of the MOS field effect transistor. When information is read from the device, a voltage, for example, of about +5 volts, should be supplied to the control gate of the MOS field effect transistor. In such a semiconductor memory device, it is necessary to detect whether the supplied voltage is low, for example 5 volts, or high, for example 25 volts. It is also necessary to control a program circuit or the read out circuit so as to keep the program circuit or the read out circuit in an operating state or in a non operating state. When a voltage having these two different values is detected, the low voltage has a value of about 5 volts, therefore a typical MOS field effect transistor will be placed in a conductive state even if as little as 5 volts is applied thereto. Therefore, a special design is required for the voltage detection circuit.
When a voltage detection circuit is constructed using a MOS FET (Metal-Oxide-Semiconductor Field Effect Transistor), a series circuit consisting of a depletion type MOS FET and an enhancement type MOS FET, that is, an enhancement/depletion mode inverter circuit, has been conventionally used. In this conventional voltage detection circuit, the current in the enhancement type MOS FET used as a driver should be selected to be smaller than the current in the depletion type MOS FET, so that when the supplied voltage is low, for example 5 volts, the enhancement type MOS FET is kept in an on state, while the voltage level at a connection point between the two MOS FETs is kept at a relatively high level. When the supplied voltage is high, for example 25 volts, the enhancement type MOS FET is placed in the complete on state, and the voltage level at the connection point between the two MOS FETs is maintained at the sufficiently low level. Therefore, the supplied voltage level is detected by using the voltage level difference at the connection of the two MOS FETs.
In the above-mentioned conventional voltage detection circuit, the ratio of the dimensions of the enhancement type MOS FET to the depletion type MOS FET must be strictly determined, so that the design of the circuit and the formation of the element are difficult.